1. Field of the Invention
Embodiments of the invention relate to a semiconductor chip and a semiconductor chip package comprising a semiconductor chip. In particular, embodiments of the invention relate to a semiconductor chip that requires the use of fewer option pads to operate in a dual chip mode, and a semiconductor chip package comprising the semiconductor chip.
This application claims priority to Korean Patent Application No. 10-2006-0013123, filed on Feb. 10, 2006, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
In order to achieve a relatively high degree of integration and relatively large storage capacity in a semiconductor device, a technique for mounting a plurality of individual semiconductor chips in one package has been developed. Such a technique, in which two identical semiconductor chips are mounted in one package, is disclosed, for example, in U.S. Pat. No. 6,366,487.
A dual chip package, in which two semiconductor chips are mounted, has the same package pins as a conventional chip package, such as an address pin, a control pin, and a data pin. The two semiconductor chips may be referred to individually as a first semiconductor chip and a second semiconductor chip, and each of the first and second semiconductor chips comprises a first, a second, and a third option pad. The first and second semiconductor chips disposed in the dual chip package can be used individually through the use of the three option pads of each semiconductor chip. Specifically, a dual chip enable signal is provided to each of the semiconductor chips through its first option pad, and each of the two semiconductor chips then enters a dual chip mode (i.e., a dual chip option). Further, each of the first and second semiconductor chips receives a most significant bit (MSB) address signal through its second option pad and a voltage signal from outside of the semiconductor device through its third option pad. The first or second semiconductor chip (i.e., an upper or lower semiconductor chip) is selected in accordance with the MSB address signal and the voltage signals received by the first and second semiconductor chips, respectively. For example, when the logic level of the MSB address signal is low and the logic level of the voltage signal received by the first semiconductor chip is high, the first semiconductor chip is selected, and when the logic level of the MSB address signal is high and the logic level of the voltage signal received by the second semiconductor chip is low, the second semiconductor chip is selected.
A pseudo static random access memory (PSRAM) device has properties in common with both a DRAM and an SRAM. Specifically, the PSRAM uses the internal cell structure of a dynamic random access memory (DRAM) device, and the PSRAM is externally similar to a static random access memory (SRAM) device. A cell of a PSRAM device comprises one transistor and one capacitor, like a cell of a DRAM device, so PSRAM is referred to as unit transistor random access memory (UTRAM).
Because of the high degree of integration and the large storage capacity of the dual chip package, the number of channels available for use in testing the device is restricted. Specifically, the number of test channels for a PSRAM device disposed in the dual chip package is insufficient (compared with a DRAM device disposed in the dual chip package) because a low address signal and a column address signal are supplied through separate pads of a PSRAM device.